As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in a variety of electronic devices. Generally, a solid state storage device comprises a controlling circuit and a non-volatile memory.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 is connected with a host 14 through an external bus 12. Generally, the external bus 12 is a USB bus, an SATA bus, a PCIe bus, or the like. Moreover, the solid state storage device 10 comprises a controlling circuit 101 and a non-volatile memory 105. The controlling circuit 101 is connected with the non-volatile memory 105 through an internal bus 107. According to a command from the host 14, the controlling circuit 101 stores the received write data into the non-volatile memory 105, or the controlling circuit 101 acquires a read data from the non-volatile memory 105 and transmits the read data to the host 14.
Generally, the controlling circuit 101 stores a default read voltage set. During a read cycle, the controlling circuit 101 acquires the read data from the non-volatile memory 105 according to the default read voltage set.
The controlling circuit 101 further comprises an error correction (ECC) circuit 104 and a retry table 106. The ECC circuit 104 is used for correcting the error bits of the read data. After the error bits of the read data are corrected, the corrected read data are transmitted to the host 14. However, if the ECC circuit 104 is unable to successfully correct all bits of the read data, the retry table 106 provides another retry read voltage set to the controlling circuit 101. According to the retry read voltage set, the controlling circuit 101 performs a read retry operation on the non-volatile memory 105.
The non-volatile memory 105 such as a flash memory comprises a memory array (not shown). The memory array comprises plural memory cells. In the memory array, each memory cell comprises a floating gate transistor. Depending on the amount of data to be stored in the memory cell, the flash memories may be classified into three types, i.e. a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory and a triple-level cell (TLC) flash memory. The SLC flash memory can store only one bit of data per cell. The MLC flash memory can store two bits of data per cell. The TLC flash memory can store three bits of data per cell.
Moreover, the floating gate of the floating gate transistor of each memory cell can store hot carriers. A threshold voltage (VTH) of the floating gate transistor is determined according to the amount of the stored hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the non-volatile memory 105, the amount of hot carriers to be injected into the floating gate is controlled by the controlling circuit 101. Consequently, the threshold voltage of the floating gate transistor is correspondingly changed. During a read cycle, the controlling circuit 101 provides a read voltage set to the floating gate of the floating gate transistor and determines the storing state of the floating gate transistor by judging whether the floating gate transistor is turned on.
FIG. 2A schematically illustrates the threshold voltage distribution curves of the MLC flash memory in different storing states. Each cell of the MLC flash memory has four storing states (00), (01), (10) and (11) according to the amount of the injected hot carriers. Before the hot carriers are injected into the cell, the cell is in the first storing state (00).
In practical, even if many cells are in the same storing state during the program cycle, the threshold voltages of these cells are not all identical. That is, the threshold voltages of these cells are distributed in a specified distribution curve with a median threshold voltage. As shown in FIG. 2A, the cells in the first storing state (00) have a median threshold voltage VTHE (e.g. 0V), the cells in the second storing state (01) have a median threshold voltage VTHA (e.g. 10V), the cells in the storing state (10) have a median threshold voltage VTHB (e.g. 20V), and the cells in the storing state (11) have a median threshold voltage VTHC (e.g. 30V).
Please refer to FIG. 2A again. According to the above characteristics of the MLC flash memory, a read voltage set including three read voltages Vra, Vrb and Vrc is defined. During the read cycle, the controlling circuit 101 provides the three read voltages of the read voltage set to the MLC flash memory in order to detect the storing states of the cells of the MLC flash memory.
For example, the controlling circuit 101 provides the read voltage Vrb to the non-volatile memory 105. If the threshold voltage of the cell is lower than the read voltage Vrb and the cell can be turned on, the controlling circuit 101 judges that the cell is in the first storing state (00) or the second storing state (01). Then, the controlling circuit 101 provides the read voltage Vra to the non-volatile memory 105. If the cell can be turned on, the controlling circuit 101 judges that the cell is in the first storing state (00). Whereas, if the cell cannot be turned on, the controlling circuit 101 judges that the cell is in the second storing state (01).
On the other hand, if the threshold voltage of the cell is higher than the read voltage Vrb and the cell cannot be turned on, the controlling circuit 101 judges that the cell is in the third storing state (10) or the fourth storing state (11). Then, the controlling circuit 101 provides the read voltage Vrc to the non-volatile memory 105. If the cell can be turned on, the controlling circuit 101 judges that the cell is in the third storing state (10). Whereas, if the cell cannot be turned on, the controlling circuit 101 judges that the cell is in the fourth storing state (11).
Similarly, the controlling circuit 101 can employ one read voltage to determine the storing states of one bit of the SLC flash memory. Similarly, the controlling circuit 101 can use a read voltage set including seven read voltages to determine the storing states of three bits of the TLC flash memory.
As mentioned above, the read voltage set is important for determining the storing states of the cells. However, after the non-volatile memory 105 has been used for a certain time period, the characteristics of the cells are subjected to changes. Under this circumstance, the threshold voltage distribution curves of the storing state of all cells in the non-volatile memory 105 are possibly changed, and the median threshold voltages are shifted. If the original read voltage set is still used to read the data of the non-volatile memory 105, the number of error bits increases. Since the number of the erroneously-judged cells is large, the ECC circuit 104 cannot effectively correct all of the error bits.
For solving the above drawbacks, the controlling circuit 101 uses the retry table 106 to record plural read voltage sets. If the controlling circuit 101 confirms that the ECC circuit 104 cannot effectively correct all of the error bits, the controlling circuit 101 performs a read retry operation. That is, the controlling circuit 101 acquires another read voltage set from the retry table 106. Moreover, the read voltage set is provided to the non-volatile memory 105 in order to read the data again.
FIG. 2B is a flowchart illustrating a read control method for a solid state storage device according to the prior art. During the read cycle, the controlling circuit 101 firstly performs a decoding process A. In the decoding process A, a hard decoding operation is performed according to a default read voltage set Vr_d.
That is, the controlling circuit 101 provides the default read voltage set Vr_d to the non-volatile memory 105 to acquire the read data, and the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits in the read data can be corrected, it means that the decoding operation is successfully done and the decoding process A passes. Whereas, if the error bits in the read data cannot be corrected, the decoding process A fails. Then, the controlling circuit 101 performs a read retry process.
In the read retry process, a decoding process B is firstly performed. In the decoding process B, a hard decoding operation is performed according to the retry read voltage set.
For example, m retry read voltage sets have been previously stored in the retry table 106. In the decoding process B, the controlling circuit 101 acquires a first retry read voltage set Vr_r1 from the retry table 106 to the non-volatile memory 105, and the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits in the read data can be corrected, it means that the decoding operation is successfully done and the decoding process B passes. Whereas, if the error bits in the read data cannot be corrected by using the first retry read voltage set Vr_r1, the controlling circuit 101 acquires a second retry read voltage set Vr_r2 from the retry table 106 and judges whether the decoding operation is successfully done.
As mentioned above, m retry read voltage sets Vr_r1˜Vr_rm are stored in the retry table 106. In the decoding process B, the controlling circuit 101 sequentially performs the hard decoding operation according to the predetermined sequence of the m retry read voltage sets Vr_r1˜Vr_rm in the retry table 106. If the decoding operation is successfully done according to one of the m retry read voltage sets Vr_r1˜Vr_rm, it means that the decoding process B passes. Whereas, if the data cannot be successfully decoded according to the entire of the m retry read voltage sets Vr_r1˜Vr_rm, it means that the decoding process B fails. Then, the controlling circuit 101 performs a decoding process C. Obviously, the time period of performing the decoding process B is longer than the time period of performing the decoding process A.
In the decoding process C, a soft decoding operation is performed according to the retry read voltage set. Generally, the soft decoding operation has better error correction capability than the hard decoding operation. However, in comparison with the read voltage set for the hard decoding operation, the read voltage set for the soft decoding operation contains more read voltages. Take the MLC flash memory for example. The read voltage set for the hard decoding operation contains three read voltages. In contrast, the read voltage set for the soft decoding operation contains nine read voltages. Consequently, the time period of performing the decoding process C is longer than the time period of performing the decoding process B.
For example, additional n retry read voltage sets for the soft decoding operation are stored in the retry table 106. The controlling circuit 101 sequentially performs the soft decoding operation according to the predetermined sequence of the n retry read voltage sets in the retry table 106 until the decoding operation is successfully done. If the decoding operation is successfully done according to one of the n retry read voltage sets, it means that the decoding process C passes. Whereas, if the data cannot be successfully decoded according to the entire of the n retry read voltage sets, it means that the decoding process C fails. Under this circumstance, the controlling circuit 101 generates a failed message to the host 14 to indicate that the decoding process fails.
As mentioned above, if the decoding process A fails, the controlling circuit 101 performs the read retry process. In the read retry process, the controlling circuit 101 has to perform the decoding process B at first. If the controlling circuit 101 confirms that the decoding process B fails, the controlling circuit 101 performs the decoding process C. If the controlling circuit 101 confirms that the decoding process C fails, the controlling circuit 101 issues the failed message to the host 14.
For example, m retry read voltage sets Vr_r1˜Vr_rm for the decoding process B are recorded in the retry table 106. During the decoding process B, the controlling circuit 101 sequentially reads the rn retry read voltage sets from the retry table 106 and sequentially provides the rn read voltage sets to the non-volatile memory 105. That is, the controlling circuit 101 is unable to directly acquire the suitable retry read voltage set to perform the read retry process. In other words, the controlling circuit 101 spends a long time providing unsuitable retry read voltage sets to the non-volatile memory 105. Since the time period of performing the read retry process is very long, the throughput and the read speed of the solid state storage device 10 are largely decreased.